1. Field of the Invention
As is well known in the art, each memory cell of a DRAM includes one cell transistor and one data storage capacitor. The memory cell configured in this way basically performs a read operation and a write operation. The read operation will be described below by exemplifying that a high level is stored in the memory cell.
2. Related Art
If a word line is activated to a voltage level higher than an external voltage, the cell transistor is turned on, and charge sharing occurs between the data storage capacitor and a bit line capacitor. A voltage gap (ΔV) is created between a bit line and an inverted bit line by the charge sharing. The voltage gap is amplified by a sensing operation of a bit line sense amplifier. Data sensed and amplified by the bit line sense amplifier is outputted to a segment input/output line and an inverted segment input/output line, is sensed and amplified again by a local sense amplifier, and is transferred to an outside by being loaded on a local input/output line and a global input/output line. Such a series of operations are referred to as a read operation.